1. Field of the Invention
The present invention relates generally to a test apparatus for a semiconductor memory device. More particularly, the invention relates to a test apparatus adapted to detect defects in a semiconductor memory device whose output timing varies according to various operating conditions of the device.
A claim of priority is made to Korean Patent Application No. 10-2004-0093731, filed Nov.16, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
A semiconductor memory device is typically tested by applying a test input pattern to the device and determining whether a resulting test output pattern matches an expected output pattern. Where the semiconductor memory device is defective, the test output pattern will not match the expected output pattern.
The term “test input pattern” here refers to a set of electrical input signals applied to the device, the term “test output pattern” refers to a set of electrical output signals produced by the device in response to the input signals, and the term “expected output pattern” denotes a set of reference electrical signals used to determine whether the test output pattern is acceptable.
The test input pattern and the expected output pattern are produced by a test apparatus. The test apparatus applies the test input pattern to the semiconductor memory device, and then compares the resulting test output pattern to the expected output pattern. To properly capture the test output pattern from the device, the test apparatus must sample the test output pattern according to the output timing of the semiconductor memory device. However, the output timing of the semiconductor memory device tends to vary according to various operating conditions of the device, such as its power supply voltage.
FIG. 1 shows a timing diagram for a semiconductor memory device operating under different power supply voltages. Referring to FIG. 1, the test input pattern is applied to the semiconductor memory device at a time 0.0s and the test output pattern is produced at times indicated by asterisks (*). The range of time over which data is output from the device, while operating at a particular power supply voltage, is called a “data generating region.” Data generation regions can be seen in FIG. 1 as the time periods between the first and last asterisks in each row. In FIG. 1, time is represented on the x-axis and the power supply voltage is represented on the y-axis.
As shown in FIG. 1, when the power supply voltage is increased, the device experiences a larger delay before the data generating region. For example, when the semiconductor memory device uses a power supply voltage of 2.1V, the semiconductor memory device outputs data from about 0.4 ns to about 1.5 ns. However, when using a power supply voltage of 3.9V, the semiconductor memory device outputs data from about 1.4 ns to about 2.5 ns.
While not shown, the width of the data generating region becomes smaller as the operating speed of the semiconductor memory device increases. In addition, the data generating region of the semiconductor memory device can also vary based on other conditions related to the device and its environment.
Conventional test apparatuses use strobe signals to sample the test output pattern produced by the semiconductor memory device. For instance, a comparator in the test apparatus may receive the test output pattern through a latch controlled by a strobe signal, where the latch receives the test output pattern only when the strobe signal is activated.
Because the data generation region of a semiconductor memory device can vary based on the device's operating conditions, conventional test apparatuses generally perform multiple independent trials with strobe signals having relative phase delays to ensure that the test output pattern is sampled at the right time. For example, the test apparatus may repeatedly input the test input pattern to the semiconductor device and sample the resulting test output pattern using a different strobe signal each time. If the test output pattern does not match the expected output pattern in any of the trials, the semiconductor memory device has a defect. Otherwise, if the test output pattern matches the expected output pattern in one of the trials, then the semiconductor memory device is acceptable (i.e., not defective).
FIG. 2 is a block diagram of a conventional test apparatus 1. Referring to FIG. 2, test apparatus 1 comprises a pattern generator 11, a timing generator 12, a controller 13, a driver 14, a comparator 15, and an operation determiner 16.
Pattern generator 11 generates a test input pattern and an expected output pattern for a semiconductor memory device 2. The test input pattern is applied to semiconductor memory device 2 through driver 14 under the control of controller 13, and semiconductor memory device 2 processes the test input pattern to produce a test output pattern. The term “process” here refers to any operation performed by semiconductor memory device 2 based on the test input pattern. The operation does not necessarily have to modify the test input pattern and the test output pattern does not necessarily have to be a derivative of the test input pattern per se.
Timing generator 12 generates timing signals used to control the timing of the test input pattern and a plurality of strobe signals. Timing generator 12 generates the timing signals based on timing information of the semiconductor memory device, such as its operating frequency, access time, setup and hold times, and so on. The strobe signals are driven so that they have relative phase delays from each other. In other words, the strobe signals are activated at different times.
Controller 13 transfers the expected output pattern from pattern generator 11 to comparator 15 and then, as semiconductor memory device 2 produces the test output pattern, one of the strobe signals is activated to transfer the test output pattern to comparator 15, and comparator 15 then compares the test output pattern to the expected output pattern to determine whether semiconductor memory device 2 is acceptable.
Upon comparing the expected output pattern to the test output pattern, comparator 15 generates a comparative value. A “comparative value” is an electrical signal whose logic state indicates whether the comparison determined two sets of data to be similar or dissimilar. For instance, where the expected output pattern and the test output pattern are different, comparator 15 generates the comparative value with a logic state indicating dissimilarity (e.g., a logical ‘0’). Otherwise, comparator 351 generates the comparative value with a logic state indicating similarity (e.g., a logical ‘1’).
Comparator 15 generates a comparative value each time it compares the expected output data to the test output data. In other words, comparator 15 generates a comparative value each time a new strobe signal is activated. Each successive comparative value is transferred to operation determiner 16, which analyzes the comparative value to determine whether semiconductor memory device 2 is acceptable. Upon determining that semiconductor memory device 2 is acceptable, operation determiner 16 informs controller 13.
Controller 13 uses the timing signals generated by timing generator 12 to “structure” the test input pattern and the strobe signals when respectively applying these signals to driver 14 and comparator 15. The term “structure” here refers to the process of establishing proper timing and timing relationships for the test input pattern and the strobe signals. In other words, controller 13 outputs the test pattern signals and the strobe signals according to the timing signals.
Because the conventional apparatus uses a single comparator connected to a single pin in semiconductor memory device 2, it has to send the test input data to semiconductor memory device 2 every time a new strobe signal is used to sample the test output data. As a result, the time required to test semiconductor memory device increases proportional to the number of strobe signals used in the test.